1. Field of the Invention
The present invention relates to a semiconductor device, and in particular relates to a semiconductor device which has a damascene wiring structure.
2. Description of the Related Art
Miniaturizing of the elements which form semiconductor devices is most effective for increasing the performance of the semiconductor device, and currently, the design standards for this dimension are shifting from 65 nm to 45 nm, and technology development is vigorously being promoted. Furthermore, in order to increase the performance of semiconductor devices having miniaturized structures, a groove wiring line formed by the so-called damascene method, or in other words, a damascene wiring line is necessary, wherein a wiring material layer such as a copper (Cu) layer is deposited onto an interlayer insulating layer which has grooves formed by minute machining and the wiring material layer region that is not embedded in the grooves is removed by chemical mechanical polishing (CMP) in order to reduce resistance of the wiring which connects between the elements and to minimize parasitic capacitance of the wiring. For example, refer to Japanese Patent Kokai No. H2-278822 (patent document 1).
In order to form this damascene wiring, a low inductance insulating film material which has lower relative induction than a silicon oxide film must be used as the interlayer insulating film in place of silicon oxide. Furthermore, the low inductance film will need to be made porous in order to further reduce the inductance of the interlayer insulating film. A low inductance film refers to a insulating film where the relative inductance of the silicon dioxide layer is 3.9 or less.
However, a low inductance film generally has low film density, so moisture absorbency or moisture permeability is high, and therefore, penetration of moisture into the low inductance film must be prevented. This is because penetration of even a minute amount of moisture will cause an increase in the relative inductance of the low inductance film and a drop in the reliability of the damascene wiring. Therefore, a barrier wall (seal ring) formed from the material which forms the wiring layer is generally provided along the outside edge of the semiconductor chip. For example, refer to Japanese Patent Kokai No. 2002-353307 (patent document 2).
A conventional seal ring will be described below while referring to FIG. 1 through FIG. 4C. FIG. 1 is a top view drawing of a semiconductor chip which is two dimensionally arranged on a semiconductor wafer, FIG. 2 is a partial enlarged drawing of the outside edge of the semiconductor chip, FIG. 3 is a cross-section drawing of the seal ring, and FIG. 4A through FIG. 4C are cross-section drawings of the seal ring element by manufacturing process.
As shown in FIG. 1, a seal ring 102 is formed on the outside edge of a semiconductor chip 101, or more particularly, along the dicing line so as to enclose the element forming region. The partially enlarged region 103 is shown in FIG. 2. The seal ring 102 is formed by overlaying and connecting multiple layers of conductor material which form the wiring and via plugs of the element forming region. FIG. 2 shows the top layer wiring made from damascene wiring. The seal ring 102 has a top layer barrier layer 104 made from a conductive barrier material film which is formed on the groove side wall of the interlayer insulating film of the semiconductor device and a top seal ring wiring 105 made from a wiring material film such as copper which is embedded in the groove, and the element forming region has a first top layer groove wiring line 106 and a second top layer groove wiring line 107, and a top layer barrier layer 104 is established around the perimeter. The top layer seal ring wiring 105 and both top layer wiring lines have a “dual” damascene wiring structure.
The cross-section structure of the seal ring 102 region is shown in FIG. 3. FIG. 3 is a cross section drawing viewed in the direction of arrow X1-X1 in FIG. 2. As shown in FIG. 3, a bottom insulating film 109 is formed from silicon oxide on a silicon substrate 108, and a contact hole for seal ring 110 which extends to the surface of the silicon substrate 108 is formed in a designated region of the bottom insulating film 109 of the semiconductor chip outside edge. The contact hole for seal ring 110 is formed such that the outside edge of the semiconductor chip 101 forms a square as shown in FIG. 1. Furthermore, the contact hole 110 is filled by a seal ring contact plug 111 made from a conductor such as tungsten (W). Similarly, a contact hole 112 is formed which extends to a gate electrode (not shown in the drawings) and a dispersion layer formed on the surface of the silicon substrate 108 in the element forming region, and the contact hole 112 is filled with a contact plug 113 made from a conductor such as tungsten.
Furthermore, in order to form bottom damascene wiring for the semiconductor device, a first etching stopper layer 114a, a first low inductance film 114b, and a first cap layer 114c are overlaid, this multilayer film forms a first interlayer insulating film 114, lower layer barrier layer 115 and lower layer seal ring wiring 116 are formed in the groove for the seal ring which is formed in a designated region, and contact a seal ring contact plug 111. The lower layer seal ring wiring 116 has a damascene wiring structure, and the line width is approximately 10 micrometers. Similarly, a lower layer barrier layer 115, a first lower layer groove wiring line 117, and a second lower layer groove wiring line 118 are formed in the groove for wiring established in the designated region of the first interlayer insulating film 114, and are electrically connected to the corresponding contact plug 113. The line width of both lower layer groove wiring lines are approximately 0.1 micrometers. Furthermore, the first low inductance film 114b is made from a porous methyl silsesquioxane (p-MSQ) layer with a relative inductance of approximately 2.0, and the first etching stopper layer 114a and the first cap layer 114c are insulating layers with a relative inductance rate of approximately 3, such as carbon containing silicon oxide film (SiOC film) or silicon carbide (SiC) film.
Next, a second etching stopper layer 119a, a second low inductance film 119b, and a second cap layer 119c are overlaid to form a second interlayer insulating film 119, and a third etching stopper layer 120a, a third low inductance film 120b, and a third cap layer 120c are overlaid to form a third interlayer insulating film 120. Furthermore, a groove for the seal ring is formed in the second interlayer insulating film 119 and the third interlayer insulating film 120 and a top seal ring wiring 105 which will become the dual damascene wiring structure is connected to the lower layer seal ring wiring 116, together with an upper layer barrier layer 104. Similarly, a first upper layer groove wiring 106 with a dual damascene wiring structure is formed together with an upper layer barrier layer 104 in the second interlayer insulating layer 119 and the third interlayer insulating layer 120, and the second upper layer groove wiring 107 with a damascene wiring structure is formed together with the upper layer barrier layer 104 in the third interlayer insulating layer 120. The second low inductance film 119b and the third low inductance film 120b are p-MSQ films with a relative inductance rate of approximately 2.0, and the second etching stopper layer 119a, the third etching stopper layer 120a, the second cap layer 119c and the third cap layer 120c are insulating films with a relative inductance rate of approximately 3, such as SiC films or SiOC films.
Furthermore, a fourth etching stopper layer 121 made from SiC film or SiOC film and a passivation film 122 made from a silicon oxynitride (SiON) film are formed to cover the whole surface.
With the present invention, the seal ring contact plug 111, the lower layer seal ring wiring 116, and the upper layer seal ring wiring 105 form the seal ring 102. The seal ring 102 is not restricted to only 2 layer structures consisting of a lower layer seal ring wiring and an upper layer seal ring wiring as described above, and may be similarly formed with a multilayer structure of two or more mutually connected layers.
However, when seal rings 102 are formed with a (dual) damascene wiring structure as in the aforementioned conventional example, as can be seen in FIG. 2, a bridge region 123 will form at a certain frequency in a part of the semiconductor chip 101 region between the seal ring 102 and the groove wiring in the element forming region or the electrode pad (not shown in the drawings) of the groove structure. This problem will be described below using FIG. 4A through FIG. 4C. FIG. 4A-C are cross-section drawings as viewed in the direction of arrow X2-X2 in FIG. 2. Components in FIG. 4A-C which are identical to those in FIG. 3 are assigned the same reference numerals.
As shown in FIG. 4A, a silicon oxide film is overlaid onto a silicon substrate 108 of a semiconductor wafer using a commonly known chemical vapor deposition (CVD) method, the surface is flattened using a CMP method, and a bottom insulating film 109 is formed. Contact hole 110 and contact hole 112 for the seal ring are formed in a designated region using commonly known photolithography technology and dry etching technology, and these contact holes are filled with titanium (Ti), titanium nitride (TiN), or tungsten or the like, to form seal ring contact plug 111 and contact plug 113.
Next, the first interlayer insulating film 114, comprising a first etching stopper layer 114a, a first low inductance layer 114b, and a first cap layer 114c, is formed using the CVD method or a spin coating method. Furthermore, the first cap layer 114c, the first low inductance layer 114b, and the first etching stopper layer 114a are etched in order using commonly known photolithography technology and dry etching technology to form lower layer seal ring groove 124 with a pattern width of approximately 10 micrometers, and a first lower layer wiring groove 125 and a second lower layer wiring groove 126 are formed with a pattern width of approximately 0.1 micrometers. Furthermore, a barrier material film 127 such as tantalum nitride (TaN) is formed over the whole surface using a sputtering (PVD) method, and then a wiring material film 128 such as a copper film is formed using a plating method or the like.
Next, as shown in FIG. 4B, the wiring material film 128 and the barrier material film 127 are successively subjected to CMP in order to remove the unneeded regions of the wiring material film 128 and the barrier material film 127 on the first cap layer 114c and to form the lower layer wiring with a damascene wiring structure. However, the width of the seal ring groove 124 is relatively large at approximately 10 micrometers as will be described later, so during the CMP process, a wiring depression 129 known as dishing will occur on the surface of the lower layer seal ring wiring line 116. Furthermore, when this dishing occurs, a localized high polishing pressure will be applied from the CMP polishing pad to the surface of the first interlayer insulating film 114 in the region around the lower layer seal ring wiring 116 during the CMP process, and erosion will occur in this region such that an insulating film depression 130 will be formed.
Furthermore, as shown in FIG. 4C, the second interlayer insulating film 119 comprising the second etching stopper layer 119a, the second low inductance film 119b, and the second cap layer 119c, will form on the first interlayer insulating film 114 where partial erosion has occurred, and on the lower layer seal ring wiring 116 where the aforementioned dishing has occurred, and then the third interlayer insulating film 120 comprising a third etching stopper layer 120a, a third low inductance film 120b, and a third cap layer 120c will form on the aforementioned second interlayer insulating film 119. Furthermore, using commonly known photolithography technology and dry etching technology, an upper layer seal ring groove 131 with a dual damascene structure and a first upper layer wiring groove 132 are formed on the second interlayer insulating film 119 and the third interlayer insulating film 120, and the second upper layer wiring groove 133 are formed on the third interlayer wiring film 120. Therefore, in the region above the insulating film depression 130 which occurred in a portion of the first interlayer insulating film 114 because of the aforementioned erosion, the surface position of the third interlayer insulating film 120 will be recessed below the surface position of the other regions of the third interlayer insulating film 120 where erosion did not occur.
Furthermore, when forming the conductive layer material film and the wiring material film, and when performing CMP in order to form the upper layer wiring with damascene wiring structure, the barrier material film and the wiring material film above the aforementioned insulating film depression 130 cannot be removed by CMP and will remain, and therefore a bridge region 123 will form as described in FIG. 2.